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Journals


  1. S. S. Iyer and V. Roychowdhury, “AI Computing Reaches for the Edge,“ Science, Vol. 382, No. 6668, pp. 263-264, October 2023.
  1. S. S. Nagi, U. Rathore, K. Sahoo, T. Ling, S. S. Iyer and D. Marković, "A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 x 2 Dielet With 10 um Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration," in IEEE Journal of Solid-State Circuits, 2022, doi: 10.1109/JSSC.2022.3212685.
  2. K. T. Kannan, B. Vaisband, K. Sahoo and S. S. Iyer, "An On-Chip ESD Sensor for Use in Advanced Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 7, pp. 1051-1062, July 2022, doi: 10.1109/TCPMT.2022.3177663.
  3. Zhe Wan, T. Wang, Y. Zhou, S. S Iyer, and V. Roychowdhury, "Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, no. 2, pp. 1-23, April 2022.
  1. H. Ren, Y.-T. Yang, G. Ouyang, and S. S. Iyer, "Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding," in ECS Journal of Solid State Science and Technology, vol. 10, no. 6, 2021. https://doi.org/10.1149/2162-8777/ac0a52
  1. S. S. Iyer, S. Jangam, and B. Vaisband, "Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems," in IBM Journal of Research and Development, vol. 63, no. 6, pp. 5:1-5:16, 1 Nov.-Dec. 2019.
  1. Xuefeng Gu, S. S. Iyer, "Unsupervised Learning Using Charge-Trap Transistors", IEEE Electron Device Letters, vol. 38, no. 9, pp. 1204-1207, Sept. 2017. doi: 10.1109/LED.2017.2723319
  1. Chandrasekara Kothandaraman, S. Rosenblatt, J. Safran, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo, W. Landers, J. Liu, J. A. Oakley, S. Butt, T. L. Graves-Abe, N. Robson, M. G. Farooq, D. Berger and S. S. Iyer, "Vertical channel devices enabled by through silicon via (TSV) technologies," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 9.6.1-9.6.4. doi: 10.1109/IEDM.2016.7838384
  2. Toshiaki Kirihata, J. Golz, M. Wordeman, P. Batra, G. W. Maier, N. Robson, T. L. Graves-abe, D. Berger, and S. S. Iyer, "Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 373-384, Sept. 2016. doi: 10.1109/JETCAS.2016.2547738
  3. Subramanian S. Iyer, "Heterogeneous Integration for Performance and Scaling," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no.7, pp. 973-982, Jul. 2016. doi: 10.1109/TCPMT.2015.2511626
  4. Faraz Khan, E. Cartier, C. Kothandaraman, J. C. Scott, J. C. S. Woo, and S. S. Iyer, "The Impact of Self-Heating on Charge Trapping in High- k -Metal-Gate nFETs," Electron Device Letters, IEEE , vol. 37, no. 1, pp. 88-91, Jan. 2016. doi: 10.1109/LED.2015.2504952
  5. G. Fredeman et al., "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016.
  1. Subramanian S. Iyer, T. Kirihata, "Three-Dimensional Integration: A Tutorial for Designers," in Solid-State Circuits Magazine, IEEE , vol. 7, no. 4, pp. 63-74, Fall 2015. doi: 10.1109/MSSC.2015.2474235
  2. Gregory Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee, D. Rainey, M. Sperling, M. Whalen, S. Burns, R. Tummuru, H. Ho, A. Cestero, N. Arnold, B. Khan, T. Kirihata, and S. S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873
  3. Subramanian S. Iyer, "Three-dimensional integration: An industry perspective," Materials challenges in 3D IC technology, MRS Bulletin, vol. 40, no. 3, pp. 225-232, Mar. 2015.