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Journals


  1. S. S. Iyer and V. Roychowdhury, “AI Computing Reaches for the Edge,“ Science, Vol. 382, No. 6668, pp. 263-264, October 2023.
  1. Sumeet Singh Nagi; Uneeb Rathore; Krutikesh Sahoo; Tim Ling; Subramanian S. Iyer; Dejan Markovic, "A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration," in: IEEE Journal of Solid-State Circuits ( Volume: 58, Issue: 1, January 2023), Page(s): 111 - 123, DOI: 10.1109/JSSC.2022.3212685
  2. Guangqi Ouyang; Amir Hanna; Samatha Benedict; Goutham Ezhilarasu; Arsalan Alam; Randall W. Irwin; "Comprehensive Investigation of In-Plane and Out-of-Plane Die Shift in Flexible Fan-Out Wafer-Level Packaging Using Polydimethylsiloxane," Subramanian S. Iyer, IEEE Transactions on Components, Packaging and Manufacturing Technology ( Volume: 12, Issue: 10, October 2022) Page(s): 1692 - 1701, DOI: 10.1109/TCPMT.2022.3207031
  3. K. T. Kannan, B. Vaisband, K. Sahoo and S. S. Iyer, "An On-Chip ESD Sensor for Use in Advanced Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 7, pp. 1051-1062, July 2022, doi: 10.1109/TCPMT.2022.3177663.
  4. Zhe Wan, T. Wang, Y. Zhou, S. S Iyer, and V. Roychowdhury, "Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, no. 2, pp. 1-23, April 2022.
  1. Yu-Tao Yang; Chaowei Hu; Peng Zhang; Niloofar Shakoorzadeh; Haoxiang Ren; Ni Ni; Kang L. Wang; Subramanian S. Iyer, "Nb-Based Superconducting Silicon Interconnect Fabric for Cryogenic Computing Applications," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), DOI: 10.1109/ECTC32696.2021.00250
  2. Kalappurakal Thankappan, Kannan; Iyer, Subramanian, "An on-chip ESD sensor for use in advanced packaging,"
  3. H. Ren, Y.-T. Yang, G. Ouyang, and S. S. Iyer, "Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding," in ECS Journal of Solid State Science and Technology, vol. 10, no. 6, 2021. https://doi.org/10.1149/2162-8777/ac0a52
  4. Ujash Shah; Matthew Ma; Michael T. Barako; Avram Bar-Cohen; Subramanian S. Iyer; Timothy S. Fisher, "Experimental Demonstration of Pressure-Driven Flash Boiling for Transient Two-Phase Cooling", in: IEEE Transactions on Components, Packaging and Manufacturing Technology ( Volume: 11, Issue: 10, October 2021), Page(s): 1604 - 1614, DOI: 10.1109/TCPMT.2021.3085876
  5. Sivachandra Jangam; Subramanian Iyer, "Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration," IEEE Transactions on Components, Packaging and Manufacturing Technology ( Volume: 11, Issue: 5, May 2021) IEEE Transactions on Components, Packaging and Manufacturing Technology ( Volume: 11, Issue: 5, May 2021), Date of Publication: 23 April 2021 ISSN Information, Page(s): 727 - 738, DOI: 10.1109/TCPMT.2021.3075219
  6. Elaheh Rabiei; Lixian Huang; Hao-Yu Chien; Arjun Earthperson; Mihai A. Diaconeasa; Jason Woo; Subramanian Iyer; Mark White; Ali Mosleh, "Method and software platform for electronic COTS parts reliability estimation in space applications," Volume 235, Issue 5, DOI: 10.1177/1748006X21998231
  7. Rachel M. Brewer; En Xia Zhang; Mariia Gorchichko; Peng Fei Wang; Jonathan Cox; Steven L. Moran; Dennis R. Ball; Brian D. Sierawski; Daniel M. Fleetwood; Ronald D. Schrimpf; Subramanian S. Iyer; Michael L. Alles, "Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors," in: IEEE Transactions on Nuclear Science ( Volume: 68, Issue: 5, May 2021) Page(s): 677 - 686, DOI: 10.1109/TNS.2021.3059594
  1. Sepideh Nouri; Subramanian S. Iyer, "Non-Volatile Wideband Frequency Tuning of a Ring-Oscillator by Charge Trapping in High·k Gate Dielectric in 22nm CMOS," in: IEEE Electron Device Letters ( Volume: 42, Issue: 1, January 2021) Page(s): 110 - 113, DOI: 10.1109/LED.2020.3036080
  2. SivaChandra Jangam; Subramanian S. Iyer, "A Signaling Figure of Merit (s-FoM) for Advanced Packaging," IEEE Transactions on Components, Packaging and Manufacturing Technology ( Volume: 10, Issue: 10, October 2020), Page(s): 1758 - 1761, DOI: 10.1109/TCPMT.2020.3022760
  3. Saptadeep Pal; Daniel Petrisko; Rakesh Kumar; Puneet Gupta, "Design Space Exploration for Chiplet-Assembly-Based Processors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 28, Issue: 4, April 2020), Page(s): 1062 - 1073, DOI: 10.1109/TVLSI.2020.2968904
  1. Rachel M. Brewer; Steven L. Moran; Jonathan Cox; Brian D. Sierawski; Michael W. McCurdy; En Xia Zhang; Subramanian S. Iyer; Ronald D. Schrimpf; Michael L. Alles; Robert A. Reed, "The Impact of Proton-Induced Single Events on Image Classification in a Neuromorphic Computing Architecture," in: IEEE Transactions on Nuclear Science ( Volume: 67, Issue: 1, January 2020) Page(s): 108 - 115, DOI: 10.1109/TNS.2019.2957477
  2. S. S. Iyer, S. Jangam, and B. Vaisband, "Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems," in IBM Journal of Research and Development, vol. 63, no. 6, pp. 5:1-5:16, 1 Nov.-Dec. 2019.
  3. Xuefeng Gu; Zhe Wan; Subramanian S. Iyer, "Charge-Trap Transistors for CMOS-Only Analog Memory," in: IEEE Transactions on Electron Devices ( Volume: 66, Issue: 10, October 2019) Page(s): 4183 - 4187, DOI: 10.1109/TED.2019.2933484
  4. Faraz Khan; Min Soo Han; Dan Moy; Robert Katz; Liu Jiang; Edmund Banghart; Norman Robson; Toshiaki Kirihata; Jason C. S. Woo; Subramanian S. Iyer, "Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies," in: IEEE Electron Device Letters ( Volume: 40, Issue: 7, July 2019), Page(s): 1100 - 1103, DOI: 10.1109/LED.2019.2919871
  5. Sitansusekhar Roymohapatra; Ganesh R. Gore; Akanksha Yadav; Mahesh B. Patil; Krishnan S. Rengarajan; Subramanian S. Iyer; Maryam Shojaei Baghini, "A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping," DOI: 10.1109/TCAD.2019.2907879 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 39, Issue: 5, May 2020) Page(s): 1073 - 1083,
  6. Eric Hunt-Schroeder; Darren Anand; John Fifield; Michael Roberge; Dale Pontius; Mark Jacunski; Kevin Batson; Matthew Deming; Faraz Khan; Dan Moy; Alberto Cestero; Robert Katz; Zakariae Chbili; Edmund Banghart; Liu Jiang; Balaji Jayaraman; Rajesh R. Tummuru; Ramesh Raghavan; Amit Mishra; "14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing," in: IEEE Solid-State Circuits Letters ( Volume: 1, Issue: 12, December 2018), Page(s): 233 - 236, DOI: 10.1109/LSSC.2019.2899519
  1. Ambhore, Pranav;Mani, Karthick;Beekley, Brett;Malik, Nishant;Schjølberg-Henriksen, Kari;Iyer, Subramanian;Fisher, Timothy, "The Synergistic Roles of Temperature and Pressure in Thermo-Compression Bonding of Au," ECS Transactions, Volume 86, Number 5, Pranav Ambhore et al 2018 ECS Trans. 86 129, DOI 10.1149/08605.0129ecst
  2. Takafumi Fukushima; Arsalan Alam; Amir Hanna; Siva Chandra Jangam; Adeel Ahmad Bajwa; Subramanian S. Iyer; "Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration," IEEE Transactions on Components, Packaging and Manufacturing Technology ( Volume: 8, Issue: 10, October 2018), Page(s): 1738 - 1746, DOI: 10.1109/TCPMT.2018.2871603
  3. Yuan Du; Li Du; Xuefeng Gu; Jieqiong Du; X. Shawn Wang; Boyu Hu; Mingzhe Jiang; Xiaoliang Chen; Subramanian S. Iyer; Mau-Chung Frank Chang, "An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)," in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 38, Issue: 10, October 2019) Page(s): 1811 - 1819, DOI: 10.1109/TCAD.2018.2859237
  4. Balaji Jayaraman; Derek Leu; Janakiraman Viraraghavan; Alberto Cestero; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; Toshiaki Kirihata; Subramanian S. Iyer, "80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity," in: IEEE Journal of Solid-State Circuits ( Volume: 53, Issue: 3, March 2018), Page(s): 949 - 960, DOI: 10.1109/JSSC.2017.2784760
  1. Xuefeng Gu, S. S. Iyer, "Unsupervised Learning Using Charge-Trap Transistors", IEEE Electron Device Letters, vol. 38, no. 9, pp. 1204-1207, Sept. 2017. doi: 10.1109/LED.2017.2723319
  2. Arvind Kumar, Zhe Wan, Winfried W. Wilcke, Subramanian S. Iyer, "Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration," in ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 13, Issue 3, DOI : 10.1145/297674
  1. Chandrasekara Kothandaraman, S. Rosenblatt, J. Safran, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo, W. Landers, J. Liu, J. A. Oakley, S. Butt, T. L. Graves-Abe, N. Robson, M. G. Farooq, D. Berger and S. S. Iyer, "Vertical channel devices enabled by through silicon via (TSV) technologies," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 9.6.1-9.6.4. doi: 10.1109/IEDM.2016.7838384
  2. Faraz Khan; Eduard Cartier; Jason C. S. Woo; Subramanian S. Iyer, "Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible MultiplnmeProgrammable Non-Volatile Memory Element for High-k-Metal-Gate CMOS Technologies," in: IEEE Electron Device Letters ( Volume: 38, Issue: 1, January 2017) Page(s): 44 - 47, DOI: 10.1109/LED.2016.2633490
  3. Liheng Zhu; Yasmine Badr; Shaodi Wang; Subramanian Iyer; Puneet Gupta, "Assessing Benefits of a Buried Interconnect Layer in Digital Designs," in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 36, Issue: 2, February 2017) Page(s): 346 - 350, DOI: 10.1109/TCAD.2016.2572144
  4. Toshiaki Kirihata, J. Golz, M. Wordeman, P. Batra, G. W. Maier, N. Robson, T. L. Graves-abe, D. Berger, and S. S. Iyer, "Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 373-384, Sept. 2016. doi: 10.1109/JETCAS.2016.2547738
  5. Subramanian S. Iyer, "Heterogeneous Integration for Performance and Scaling," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no.7, pp. 973-982, Jul. 2016. doi: 10.1109/TCPMT.2015.2511626
  6. Faraz Khan, E. Cartier, C. Kothandaraman, J. C. Scott, J. C. S. Woo, and S. S. Iyer, "The Impact of Self-Heating on Charge Trapping in High- k -Metal-Gate nFETs," Electron Device Letters, IEEE , vol. 37, no. 1, pp. 88-91, Jan. 2016. doi: 10.1109/LED.2015.2504952
  7. G. Fredeman et al., "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016.
  1. Faraz Khan; Eduard Cartier; Chandrasekara Kothandaraman; J. Campbell Scott; Jason C. S. Woo; Subramanian S. Iyer, "The Impact of Self-Heating on Charge Trapping in High-k-Metal-Gate nFETs," in: IEEE Electron Device Letters ( Volume: 37, Issue: 1, January 2016), Page(s): 88 - 91, DOI: 10.1109/LED.2015.2504952
  2. Subramanian S. Iyer, T. Kirihata, "Three-Dimensional Integration: A Tutorial for Designers," in Solid-State Circuits Magazine, IEEE , vol. 7, no. 4, pp. 63-74, Fall 2015. doi: 10.1109/MSSC.2015.2474235
  3. Gregory Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee, D. Rainey, M. Sperling, M. Whalen, S. Burns, R. Tummuru, H. Ho, A. Cestero, N. Arnold, B. Khan, T. Kirihata, and S. S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873
  4. Subramanian S. Iyer, "Three-dimensional integration: An industry perspective," Materials challenges in 3D IC technology, MRS Bulletin, vol. 40, no. 3, pp. 225-232, Mar. 2015.