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How Chip Designers Are Breaking Moore’s Law

If microchips were cities, the new, industrywide strategy for making them better could be summed up in one word: sprawl. In some case, the chips inside our most powerful devices are taking up so much real estate they hardly qualify as “micro” anymore. One way engineers are making this happen is by piling microchips atop one another. It’s like urban infill, only instead of building towering new apartment blocks, the usually pancake-flat tiles of silicon inside of computers are becoming multistory, with the circuitry used for functions such as memory, power management and graphics stacked on top...

Micron Is First to Deliver 3D Flash Chips With More Than 200 Layers

232-layer NAND makes tiny 2-terabyte products that deliver data 50 percent faster: Boise, Idaho–based memory manufacturer Micron Technology says it has reached volume production of a 232-layer NAND flash-memory chip. It’s the first such chip to pass the 200-layer mark, and it’s been a tight race. Competitors are currently providing 176-layer technology, and some have said they are on track to follow Micron’s skyward move or already have working chips in hand. The new Micron tech as much as doubles the density of bits stored per unit area versus competing chips, packing in 14.6 gigabits per square...

Professor Subramanian Iyer Weighs In - 3DInCites Podcast: "Conversations About What We Learned From ECTC 2022"

[Listen to the exclusive interview by clicking "Read more" below!] In Part 1 of ECTC 2022 coverage, Françoise catches up with some of the industry visionaries at key companies in the microelectronics space, as well as 3D technology research institutes to find out what they shared and learned at ECTC 2022. Subramanian (Subu) Iyer, of the UCLA CHIPS program, explains why he believes chiplets should be called dielets. Why chiplets aren’t where they need to be yet to match the performance of monolithic chips, and the work they are doing at UCLA to...

NIST Awards Funding to Strengthen Advanced Manufacturing for Microelectronics, Digital and Biomanufacturing

GAITHERSBURG, Md. — The U.S. Department of Commerce’s National Institute of Standards and Technology (NIST) has awarded a total of $1.2 million to four organizations to develop technology roadmaps aimed at strengthening U.S. manufacturing and innovation across industries. The projects span a wide variety of industries and technologies, from microelectronics to biomanufacturing to building a resilient U.S. manufacturing supply chain. The lead recipients and their projects are: The Regents of the University of California, Los Angeles — $300,000 The award will bring together leaders in the microelectronic supply chain to produce a roadmap...

Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines

Recently, analog compute-in-memory (CIM) architectures based on emerging analog non-volatile memory (NVM) technologies have been explored for deep neural networks (DNNs) to improve scalability, speed, and energy efficiency. Such architectures, however, leverage charge conservation, an operation with infinite resolution, and thus are susceptible to errors. Thus, the inherent stochasticity in any analog NVM used to execute DNNs, will compromise performance. Several reports have demonstrated the use of analog NVM for CIM in a limited scale. It is unclear whether the uncertainties in computations will prohibit large-scale DNNs. To explore this critical issue of scalability, this article first presents a simulation...

TSMC R&D Chief: There’s Light at the End of the Chip Shortage

Yuh-Jier Mii started on the ground floor of Taiwan Semiconductor Manufacturing Co. in 1994 as a fabrication integration manager. Today he’s one of the Hsinchu-based company’s leaders as senior vice president of research and development. During his nearly 30 years at TSMC, he has been involved with the creation of denser and denser integrated circuits. The IEEE member is in charge of R&D for new chips built using TSMC’s 3-nanometer process node, expected to go into production later this year. (The commercial term nanometer refers to a new, improved generation of silicon semiconductor chips.) ...

2021 UCLA CHIPS Workshop Summary

The 2021 Biennial UCLA CHIPS Workshop was held at the Luskin Center at UCLA on December 1, 2021. Leaders in microelectronics, from industry and academia alike, gathered in person to discuss how academia may contribute to reshoring microelectronics in the United States. The workshop approached this task on the premise of two fundamental tenets: that innovation must be application-focused and translated into viable development, R&D support, and on-shore manufacturing; and that greater emphasis on workforce development is necessary to encourage students to study semiconductor manufacturing and packaging.

CHIPS Publications: Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding

Our journal paper "Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding" has been published by ECS Journal of Solid State Science and Technology.

Flexible Electronics Master Class #7: Flexible Hybrid Electronics 2.0 Based on Fan-Out Wafer Level Packaging

Don’t miss this opportunity to learn fan-out wafer packaging from one of the leaders in the field Subramanian Iyer, Ph.D. and Distinguished Professor at UCLA. Dr. Iyer will review the impetus of the paradigm shift in electronics packaging away from CMOS and toward hybrid packages. He will note the implications these have on Flexible Hybrid Electronics (FHE) especially the use of bare dielets, fine pitch interconnects and novel substrate materials. FHE is making a significant impact in medical and wellness electronics. The first generation of these devices generally used thinner PCBs with coarse printed...

UCLA CHIPS at ECTC/Itherm 2021

ECTC Session 2: Wafer/Panel Level System Integration and Process Advances Committee: Packaging Technologies 7. Reliability Considerations for Wafer Scale Systems Niloofar Shakoorzadeh, Randall Irwin, Yu-Tao Yang, Haoxiang Ren, Subramanian S. Iyer ECTC Session 4: Heterogeneous Integration Using 2.xD/3D Packaging Technologies Committee: Packaging Technologies 5. Novel High-Power Delivery Architecture for Heterogenous Integration Systems Kannan Kalappurakal Thankappan, Subramanian S. Iyer ECTC Session 7: 3D TSV and Interposer Committee: Interconnections 4. I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor Saptadeep Pal, Krutikesh...

SEMI Is More... Smart MedTech

Why SEMI is MORE SEMI IS MORE highlights the diverse range of platforms SEMI offers to serve the electronics manufacturing and design supply chain – from facilitating collaboration, to industry standards, advocacy, market data, networking and much more. This month we shine a spotlight on SEMI Smart MedTech and the steps being taken to help build a smarter, safer and healthier world.

HIR Workshop @ EDTM 2021

HIR Workshop @ EDTM 2021 Chengdu, China on April 8, 2021 - 9:00 am to 12:30 pm / April 7, 2021 - 6:00pm to 9:30pm PDT Heterogeneous Integration Roadmap Workshop Workshop Organizing Committee: William Chen, Subramanian Iyer, WR Bottoms, Ravi Mahajan In Collaboration with Heterogeneous Integration Roadmap Technical Working Groups Teams Schedule April 8 / April 7 09:00am–09:05am / 06:00pm-06:05pm PT      ...

UCLA CHIPS at GOMACTech 2021

Date: Tuesday, March 30 / 2:30 – 3:00 PM EDT Session No: Session 7 : Design, Power, and Reliability No: 7.4 Title: Segmented Power Delivery and Thermal Management for Heterogenous Wafer-scale Systems Date: Tuesday, March 30 - Thursday April 1 / 12:00 – 1:00 PM EDT Session No: Poster Session : Packaging, Integration, Thermal & Control Technologies Posters No: P47.2 Title: Reliability Considerations for Wafer Scale Systems No: P47.3 Title: An On-chip ESD Sensor for Dielet-based Heterogeneous Integration No: P47.4 Title: Signal and Power Delivery using Flexible,...

UCLA Showcases Nanolab and Electronic Systems at FLEX 2021 Virtual Conference

At a major conference this week for industry and academia to share the latest technical breakthroughs on electronics applications, a team of UCLA researchers and scientists demonstrate the university’s latest innovation. UCLA’s shared research infrastructure, such as the state-of-the-art Nanofabrication Laboratory (Nanolab) co-operated by the California NanoSystems Institute (CNSI) and the UCLA Samueli School of Engineering, create the ideal collaborative atmosphere to conduct advanced research. The partnership has led to breakthroughs such as “FlexTrate” — a flexible biocompatible platform for electronic devices and systems that was developed at the UCLA Center for Heterogeneous Integration...

Congratulations to the IMAPS 2020 Society Award Winners!

The Daniel C. Hughes, Jr. Memorial Award is the highest, most prestigious annual technical honor, and is awarded to the individual who has the greatest combination of technical achievements related to microelectronics, combined with outstanding contributions supporting the microelectronics industry, academic achievement, or support and service to IMAPS.

Emerging Memories May Never Go Beyond Niche Applications

It is time for a frank discussion about emerging memories. Many have now been percolating for decades with the promise of displacing established incumbents such as DRAM and NAND flash. But will emerging memories ever see the light of day? Despite research breakthroughs and new patents on potentially disruptive technologies, DRAM and NAND technologies continue to advance despite the slowing of Moore’s Law. That means the goal posts are always moving for the possible replacements. MRAM, ReRAM, FRAM and PCRAM are often discussed in the context of emerging use cases such as automotive, industrial Internet of things...

Heterogeneous Integration - Why Is It Becoming Such a Big Deal and How Does It Affect Electron Device Development (Recording)

If you take any printed circuit board (PCB) today, it is already more than likely an example of heterogeneous Integration. So in truth, Heterogeneous Integration is not really new. So why this new found hype? In this talk, we describe what needs to be different about heterogeneous integration by trying to address some key differences between the new heterogeneous integration and the ones of bygone eras: What is the optimal size of chiplets or more correctly dielets; what is the optimal pitch at which they need to be connected; How close must we connect them; and how large should we...

Goodbye, Motherboard. Hello, Silicon-Interconnect Fabric By Puneet Gupta and Subramanian S. Iyer (IEEE Spectrum)

The need to make some hardware systems tinier and tinier and others bigger and bigger has been driving innovations in electronics for a long time. The former can be seen in the progression from laptops to smartphones to smart watches to hearables and other “invisible” electronics. The latter defines today’s commercial data centers—megawatt-devouring monsters that fill purpose-built warehouses around the world. Interestingly, the same technology is limiting progress in both arenas, though for different reasons.

FlexTech News: Project Updates, FLEX 2020 Recap, and COVID-19

Making More of Moore’s Law

UCLA researchers have a plan to redesign computer chips from the ground up to make smaller, cheaper, and more dynamic electronic devices. If you crack open any of the electronic devices you use on a daily basis— your phone, smartwatch, tablet, TV, instant pot or microwave— you’ll see a landscape reminiscent of a miniscule city map. Computer chips, each dotted with microscopic transistors, are arranged like buildings on the green grid of a circuit board. The view you see is roughly how the insides of computers have looked for the past half century. But UCLA researchers at...

Semiconductor Engineering Article: Making microvias in packages; flexible fan-out.

Flexible fan-out At ECTC, the University of California at Los Angeles (UCLA) described more details about a fan-out wafer-level packaging integration process using a flexible substrate. In the works for some time, UCLA refers to its flexible substrate technology as FlexTrate. In its latest work, researches demonstrated a foldable display with LED dielets. Flexible hybrid electronics are gaining steam in the market. The technology enables the integration of dies on a flexible organic substrate. But there are some challenges with the technology.

5 Most Popular T-CPMT Articles according to Xplore® usage statistics March 2019

Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration Takafumi Fukushima ; Arsalan Alam ; Amir Hanna ; Siva Chandra Jangam ; Adeel Ahmad Bajwa ; Subramanian S. Iyer Publication Year: 2018, Page(s):1738 - 17463-D Printed Metal-Pipe Rectangular Waveguides Mario D’Auria ; William J. Otter ; Jonathan Hazell ; Brendan T. W. Gillatt ; Callum Long-Collins ; Nick M. Ridler ; Stepan Lucyszyn Publication Year: 2015, Page(s):1339-1349 An Electrohydrodynamic Jet Printing System With Metal Nanoparticle-Based Ink: Experimental Evaluation Jung Woo Sohn ; Chulhee...

3DInCities "A Race to the Finish: Announcing the Winners of the 2019 3D InCites Awards"

Research Institute of the Year: UCLA’s CHIPS Lab

3DInCites "System-level Scaling: UCLA’s Answer to Extending Moore’s Law" by Francoise von Trapp

“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about scaling the system.” ~ Excerpt from the letter to attendees of the CHIPS kick-off meeting at UCLA. This is the mission of the new Center for Heterogeneous Integration and Performance Scaling (CHIPS) that was launched with a kick-off meeting at UCLA on November 2, 2015.

Flexible, Heterogeneously Integrated Wireless Powered System for Implantable Applications using FlexTrate

Medical implants today are often rigid & bulky causing discomfort and infections with prolonged usage. Hence there is a need for implants made using elastomeric packaging materials that closely match the flexibility of human tissue so as to conform to any surface inside the body with relative ease. Ideally, such implants should also be operated wirelessly so as to avoid bulky wires for signal & power or periodic surgeries for battery replacements. Conventional approaches to flexible electronics which rely on sheet- level roll-roll processing and printed interconnects cannot face up to this task as the...

Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrate TM ) was used to assemble 625 dies with co-planarity and tilt <1µm, average die-shift of 3.28 µm with σ < 2.23 µm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in...

IEEE 68th Electronic Components and Technology Conference Best Student Paper Award

Siva Chandra Jangam (Advisor: Prof. Subramanian Iyer, UCLA Center for Integration and Performance Scaling (CHIPS)) won the ECTC Best Student Paper Award for the paper titled “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” at the 2018 IEEE 68th Electronic Components and Technology Conference held in San Diego, CA. This latest work describes the performance and power benefits of the Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF) proposed by a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. Dramatic improvements in bandwidth, latency, and power are achievable...

Characterization of Fine Pitch Interconnections (<=10um) on Silicon Interconnect Fabric for Heterogeneous Integration - Siva Jangam

The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets. We propose a fine-pitch integration scheme where dielets are attached to the Si-IF with fine-pitch interconnects (≤10 µm) at short inter-dielets spacings (≤100 µm) using direct metal-metal Thermal Compression Bonding process (TCB). As a result, short links on Si-IF (≤ 500 µm) are used for inter-dielet communication, reducing the latency to ≤ 35 ps. We experimentally demonstrated the measured insertion loss in these short Si-IF links (≤ 500 µm) is ≤2 dB for frequencies up to 30 GHz. As a result, we show that assemblies on...

Dynamically Controlled Flow Loop to Benchmark Rapid Transient Cooling Utilizing Flash Boiling for High Heat Flux Electronic Systems - Ujash Shah

Transient cooling of high-heat-flux components presents significant challenges. Flash cooling is a promising approach to mitigate temperature spikes due to episodic heat pulses in electronic components. We present a flow loop concept that provides a flexible and reliable setup to quantify and benchmark flash cooling. The testbed is dynamically controlled through LabVIEW workbench using a micro-controller to manage the transient response of the system. The quick response of the loop is achieved with the help of flow control components with a response time of a few milliseconds. The setup is compatible with fluids for...

Prof. Subramanian S. Iyer and Prof. Alan N. Willson, Jr. have awarded to the rank of NAI Fellows.

The 2017 National Academy of Inventors (NAI) Fellows Selection Committee and Board of Directors have awarded Dr. Subramanian S. Iyer and Dr. Alan N. Willson, Jr., of the Electrical & Computer Engineering Department, to the rank of NAI Fellows, the nominations of which were submitted by Dr. Asad M. Madni. Both have been chosen as they have “demonstrated a highly prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.” The Fellows Induction Ceremony will be held on April 5, 2018 at...

Packageless processors; improving AI accuracy; superconductivity rules. BY: ANN STEFFORA MUTSCHLER

Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. However, a team of researchers from the Department of Electrical and Computer Engineering from the University of California, Los Angeles along with colleagues from the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by...

4 Strange New Ways to Compute

Prof. Gupta's invited talk on packageless computing systems at International Conference on Rebooting Computing gets covered on IEEE Spectrum website.

Universities Obtain New Funding from Nano-Bio Manufacturing Consortium

University of California at Los Angeles: UCLA will partner with i3 Electronics of Binghamton, NY to investigate the use of Fan-Out Wafer Level Packaging (FOWLP) methods as a new way to build versatile, biocompatible physically-flexible heterogeneous electronic systems. FOWLP is a relatively new packaging process that gaining widespread use in portable devices such as smart phones. It offers the advantages of true heterogeneous integration of different dies, including high performance electronics, tight pitch interconnects, and components (such as low profile passives) with a short turn-around, scalable, manufacturing process.

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?

Making 2.5D, Fan-Outs Cheaper

Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.

IFTLE 301 Are Silicon Circuit Boards in our Future?

The CHIPS mission is to interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes that will shrink system footprint and improve power and performance.

ECTC 2016: Is the Life after Moore’s Law?

Is Moore’s Law dead or not? It depends on your perspective. Last week at ECTC 2016, Rozalia Beica, Dow Electronic Materials, gathered a prestigious group of senior executives from the world’s leading microelectronics research institutes to discuss Life after Moore’s Law. Panelists included Marie-Noelle Semeria, CEA-Leti; Dim Lee Kwong, IME; Luc van den hove, imec; CP Wong, NCAP; and Subu Iyer, UCLA CHIPS. Each discussed the strategy they will pursue to continue innovations for next-generation computing technologies, with or without Moore’s Law.

Semiconductor Engineering “Why Use A Package” by Ed Sperling

UCLA’s Subramaniam Iyer believes the industry needs to rethink its future direction.