Classical Si based CMOS scaling has achieved a 1000X reduction in feature size over the last five decades and is still scaling even though development and manufacturing costs are rising. However, other aspects of the system such as the package and board have not kept up. Integrating more and increasingly diverse function on a single die – SOC technology – is also getting more expensive and complex. The barrier to entry has become exorbitant while the time to product has grown longer. CHIPS will develop technologies to circumvent these problems with a radically different way of assembling systems.

Figure 1. Scaling minimum chip feature (~1000x) in silicon (blue) as a function of time, and the scaling of package features (~4x) in the same time frame (red). We have used chip-to-package interconnects (bump pitch) in this example, but the results hold true for other package and board-related features as well.