Interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes, that will shrink system footprint and improve power and performance.
Our journal paper "Mechanism and Process Window Study for Die-to-Wafer (D2W) Hybrid Bonding" has been published by ECS Journal of Solid State Science and Technology.
Don’t miss this opportunity to learn fan-out wafer packaging from one of the leaders in the field Subramanian Iyer, Ph.D. and Distinguished Professor at UCLA. Dr. Iyer will review the impetus of the paradigm shift in electronics packaging away from CMOS and toward hybrid packages. He will...
ECTC Session 2: Wafer/Panel Level System Integration and Process Advances Committee: Packaging Technologies 7. Reliability Considerations for Wafer Scale Systems Niloofar Shakoorzadeh, Randall Irwin, Yu-Tao Yang, Haoxiang Ren, Subramanian S. Iyer ECTC Session 4: Heterogeneous Integration Using 2.xD/3D Packaging Technologies Committee: Packaging Technologies...