A. Kuchhangi, H. Ren, K. Sahoo, and S. S. Iyer, “Large Wafer GaN on Silicon Reconstitution with Gold-to-Gold Thermocompression Bonding,” in 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), May 2023, pp. 1633–1637. doi: 10.1109/ECTC51909.2023.00277.
H. Ren, K. Sahoo, T. Xiang, G. Ouyang, and S. S. Iyer, “Demonstration of a Power-efficient and Cost-effective Power Delivery Architecture for Heterogeneously Integrated Wafer-scale Systems,” in 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), May 2023, pp. 1614–1621. doi: 10.1109/ECTC51909.2023.00274.
K. T. Kannan, B. Vaisband, K. Sahoo and S. S. Iyer, "An On-Chip ESD Sensor for Use in Advanced Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 7, pp. 1051-1062, July 2022, doi: 10.1109/TCPMT.2022.3177663.
P. Venkatesh, R. Irwin, A. Alam, M. Molter, A. Kapoor, B. Gaonkar, L. Macyszyn, M. Selvan Joseph, S. S. Iyer, "Smartphone App-Enabled Flex sEMG Patch using FOWLP," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), June 2022.
H. Ren, S. Pal, G. Ouyang, R. Irwin, Y.-T. Yang, S. S. Iyer, "TSV-less Power Delivery for Wafer-scale Assemblies and Interposers," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), June 2022.
Yu-Tao Yang, Haoxiang Ren,Chaowei Hu, Peng Zhang, Ni Ni, Kang L. Wang, and Subramanian S. Iyer, “Emerging Applications Using Niobium-based Superconducting Silicon Interconnect Fabric,” 7th Annual Critical Material Conference (CMC), Arizona, Apr. 2022.
N. S. Chase, R. Irwin, Y. T. Yang, H. Ren and S. S. Iyer, "Reliability Considerations for Wafer Scale Systems," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, pp. 84-89, doi: 10.1109/ECTC32696.2021.00025.
N. Shakoorzadeh, and S. S. Iyer, "Reliability Considerations for Wafer Scale Systems," GOMACTech Conference, March 2021.
R. Irwin, and S. S. Iyer, "Signal and Power Delivery using Flexible, High-Speed Connectors and Segmented PCBs for System-on-Wafer Applications," GOMACTech Conference, March 2021.
Rachel M. Brewer, J. Cox, D. R. Ball, S. Moran, B. D. Sierawski, P. F. Wang, E. X. Zhang, D. M. Fleetwood, R. D. Schrimpf, S. S. Iyer, and M. L. Alles, "Total Ionizing Dose Response of 22nm FDSOI Charge-Trap Transistors", 2020 IEEE Nuclear and Space Radiation Effects Conference, Dec. 1-4, 2020, Santa Fe, NM. (Accepted)
K. T. Kannan and S. S. Iyer, "Deep Trench Capacitors in Silicon Interconnect Fabric," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 2295-2301, doi: 10.1109/ECTC32862.2020.00358.
A. Dasgupta, A. Alam, G. Ouyang, S. Jangam and S. S. Iyer, "Antenna on Silicon Interconnect Fabric," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 1788-1794, doi: 10.1109/ECTC32862.2020.00279.
E. Hunt-Schroeder, D. Anand, D. Pontius, M. Roberge, D. Moy, E. Banghart, N. Robson, F. Khan, T. Kirihata, S. Ventrone, "Design and Development Challenges of Charge Trap Transistor Memories", GOMACTech, 2020.
Steven Moran, J. Cox, Z. Wan, R. Brewer, E. X. Zhang, B. Sierawski, J. Woo, and S. S. Iyer, "Impacts of Perturbation on a Charge Trap Transistor Analog Neural Network", GOMACTech-20, Microelectronics for a New Decade: Global Competition and Near-Peer Challenges, March 16-19, 2020, San Diego, CA. (Accepted)
Arsalan Alam, Michael Molter, and Subramanian S. Iyer, "Development of FlexTrateTM using Fan-Out-Wafer-Level-Packaging (FOWLP) and to demonstrate fully integrated multi-channel flexible surface Electromyography (sEMG) system," Flex 2020, San Jose, CA, February 24-27, 2020
Rachel Brewer, S. Moran, J. Cox, B. Sierawski, M. McCurdy, S. S. Iyer, M. Alles, and R. Reed, "The impact of proton-induced single events on image classification in a neuromorphic architecture," 2019 IEEE Nuclear and Space Radiation Effects Conference, July 8-12, 2019, San Antonio, TX.
Kannan K. Thankappan, B. Vaisband, S. S. Iyer, "On-Chip ESD Monitor", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
Niloofar Shakoorzadeh, S. Jangam, P. Ambhore, H. Chien, A. Hanna, S. S. Iyer, "Reliability Studies of Si Interconnect Fabric (Si-IF)", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
Subramanian S. Iyer, S. Jangam, and B. Vaisband, "From Homogeneous SoCs to Heterogeneous SoWs," Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2019.
Steven Moran, J. Cox, R. Brewer, B. Sierawski, and S. S. Iyer, "Radiation Effects on Brain-Inspired Computing," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 25-28, 2019, Albuquerque, NM.
Zhe Wan, S. Moran, J. Cox, X. Gu, V. Rowchowdhury, and S. S. Iyer, "Characterization Approaches to Test the Robustness of Neuromorphic Systems," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 25-28, 2019, Albuquerque, NM.
Arsalan Alam and S. S. Iyer, "Heterogeneously Integrated Foldable Display on Elastomeric Substrate Based on Fan-Out Wafer Level Packaging", Flex 2019, February 18-21, 2019, Monterey, CA.
Saptadeep Pal, D. Petrisko, M. Tomei, P. Gupta, S. S. Iyer, and R. Kumar, "Architecting Waferscale Processors: A GPU Case Study", in 25th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 16-20, 2019, Washington D.C., USA.
Goutham Ezhilarasu, A. Hanna, R. Irwin, A. Alam, and S. S. Iyer, "A Flexible, Heterogeneously Integrated Wireless Powered System for Bio-Implantable Applications using Fan-Out Wafer-Level Packaging," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 29.7.1-29.7.4. doi: 10.1109/IEDM.2018.8614705
Bau Pham, B. Gaonkar, W. Whitehead, S. Moran, Q. Dai, L. Macyszyn, and V. R. Edgerton, "Cell Counting and Segmentation of Immunohistochemical Images in the Spinal Cord: Comparing Deep Learning and Traditional Approaches," 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Jul. 2018.
Takafumi Fukushima, Y. Susumago, H. Kino, T. Tanaka, A. Alam, A. Hanna, and S. S. Iyer "Self-Assembly Technologies for FlexTrate™," IEEE 68th IEEE Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, CA.
Rachel M. Brewer, S. Moran, J. Cox, M. McCurdy, R. Erbrick, M. Alles, R. Reed, S. S. Iyer, and B. Sierawski, "Proton-Induced Classification Changes in a Neuromorphic Computing System," 2018 Single Event Effects (SEE) Symposium, May 20-24, 2018, San Diego, CA.
B. Vaisband, A. Bajwa, and S. S. Iyer, “Network on Interconnect Fabric,” Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2018.
Saptadeep Pal, D. Petrisko, A. Bajwa, P. Gupta, S. S. Iyer, and R. Kumar "A Case for Packageless Processors", 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 24-28, 2018, Vienna, Austria.
R. M. Walker, L. Rieth, S. S. Iyer, A. A. Bajwa, J. Silver, T. Ahmed, N. Tasneem, M. Sharma, A. Gardner, "Integrated neural interfaces," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017, pp. 1045-1048. doi: 10.1109/MWSCAS.2017.8053106
Arsalan Alam, T. Fukushima, A. Hanna, S. C. Jangam, A. Bajwa, and S. S. Iyer, "FlexTrate™: For next generation high performance flexible systems", FlexTech Flexible & Printed Electronics Conference & Exhibition (2017 Flex), June 19-22, 2017, Monterey, CA.
Chandrasekara Kothandaraman, S. Rosenblatt, J. Safran, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo, W. Landers, J. Liu, J. A. Oakley, S. Butt, T. L. Graves-Abe, N. Robson, M. G. Farooq, D. Berger and S. S. Iyer, "Vertical channel devices enabled by through silicon via (TSV) technologies," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 9.6.1-9.6.4. doi: 10.1109/IEDM.2016.7838384
Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "A New Flexible Device Integration Technology Based on Fan-Out Wafer-Level Packaging", Printed Electronics USA in IDTechEx show, p.96, Nov. 16-17, 2016, Santa Clara, CA, Academic Posters.
Brittany Hedrick, V. Sukumaran, B. Fasano, C. Tessler, J. Garant, J. Lubguban, S. Knickerbocker, M. Cranmer, K. Ramachandran, I. Melville, D. Berger, M. Angyal, R. Indyk, D. Lewison, C. Arvin, L. Guerin, M. Cournoyer, M. P. L. Ouellet, J. Audet, F. Baez, S. Li, and S. S. Iyer, "End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 283-288. doi: 10.1109/ECTC.2016.261
Toshiaki Kirihata, J. Golz, M. Wordeman, P. Batra, G. W. Maier, N. Robson, T. L. Graves-abe, D. Berger, and S. S. Iyer, "Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 373-384, Sept. 2016. doi: 10.1109/JETCAS.2016.2547738
Gregory Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee, D. Rainey, M. Sperling, M. Whalen, S. Burns, R. Tummuru, H. Ho, A. Cestero, N. Arnold, B. Khan, T. Kirihata, and S. S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873
Muqta G. Farooq, G. La. Rosa, F. Chen, P. Periasamy, T. Graves-Abe, C. Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, J. Safran, S. Ghosh, S. Mittl, D. Ioannou, C. Graas, D. Berger, and S. S. Iyer, "Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability," 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. 4C.1.1-4C.1.8. doi: 10.1109/IRPS.2015.7112732